Satendra Mane

Assistant Professor
Electronics and Telecommunication Engineering
Life Member ISTE
Life Member IETE

M.E. (Electronics), Mumbai University 2002
B.E. (Electrical), Mumbai University 1996


Teaching Experience: 28 Years
Research/ Industrial Experience: 2 Years
Technical Papers Published: 11
Industry Projects Executed: 1

Since from my childhood, I was always keen to know the electrical frameworks and used to do establishments and repairing of basic electrical appliances like tube light, electrical iron and so on. This developed a sense of enthusiasm about engineering. I completed Diploma in Electronics Engineering and I was qualified to go for the degree course. However, because of monetary issues I worked in the industry for two years. Later I realized that Degree education is important. Thus, while working as lab collaborator in Vivekanand college I finished my Degree in Electrical Engineering from SPCOE Mumbai. During my Degree course, I earned silver medal both in third and final year examinations. During this time, I got very good practical knowledge and furthermore understood that I can be a decent teacher. At that point, I joined PVPP college of Engineering as a lecturer, where I taught many undergraduate students who are now working in reputed associations in India and overseas. After working in PVPP for 18 years, I joined one of the reputed engineering institutes, Vidyalankar Institute of Technology in Mumbai. Here, I got a very good chance to learn the latest technology. In VIT, I really developed a liking and knowledge about VLSI domain and got an opportunity to learn the advanced VLSI tool like CADENCE. Thus, my journey here since the past 6 years has been amazing!

My research interests are in VLSI domain, designing, testing and verification of Digital circuits at front end level and designing and simulation of CMOS Analog circuits at the back-end level. Recently I worked with my undergraduate students on CMOS OP-AMP circuits design using CADENCE tool and successfully designed two stage CMOS OP-AMP circuit for high slew rate and three stage CMOS OP-AMP circuit for high gain and high bandwidth using 180nm Technology. My students have also been successful in implementing IOT based saline bottle for healthcare which is selected in Smart India Hackathon 2020 and the same prototype was accepted in E-Yantra 2020 at IIT Bombay. At undergraduate BE project our group of students successfully designed FIR Filter using VERILOG and implemented it using FPGA.

I always try to represent my teaching subjects in the most convenient and comprehensive way so that, there is ease of understanding of the subjects while studying. While teaching any subject I emphasis more on basic knowledge and believe in solving more numbers of numerical on the given topic. I recommend the use of learning management systems and online tools for assessments, which ensures better student learning engagement.